From AY-34 1:
The DATANET Network Processor encompasses a whole family of compact, powerful network processors which can provide Honeywell 66/DPS, 68/DPS and DPS 8 systems with largevolume network communications power. Based on Honeywell's minicomputer technology for reduced space, greater reliability, and easier serviceability, the DATANET is logically compatible with the system software and user-generated programs of the DATANET 6600 family of network processors.
The DATANET provides the variety of interfaces required by the elements and protocols of a distributed system, as well as a facility for dialog with the central system. By performing the tasks of message management and message handling, the processor relieves the central system for other processing functions. The resources of the central system are called upon only when the message is submitted for information processing. However, some networking functions (e.g., a message switch) can be accommodated by the processor without any involvement of the host processor.
It was determined the best route to implement this project was to start with the Datanet FNP. This is actually a stand-alone mini-computer (for the era) that was designed around handling large numbers of terminals performing all terminal I/O and multiplexing via a single, direct interface link to the central system.
It's been noted that it appears someone took the central system and chopped it in half to make the front end processor. Internally, it has a CPU and an IOM that interface to serial I/O cards of various types. The FNP can support asynchronous and synchronous communication links of several types.
The goal of this phase has been to implement an FNP in an FPGA development board that communicates with the DPS8M software simulator just like the real FNP would have communicated with the original central system.
This phase has been ongoing since 2021. The current state of the FNP is:
There was also a partial implementation of a software simulator for the FNP written in C. In order to better understand the implementation of the FNP before continuing on the FPGA implementation, it was decided to attempt to finish the software simulator first. A TCP/IP protocol was developed (by Charles Anthony) and implemented in a special branch of the DPS8M software simulator. The other end was implemented by Charles in the FNP C simulator and the simulator was enhanced to be able to bootload the Multics Communications System software, downloaded from the DPS8M simulator.
However, due to some significant limitations of the C implementation, and my (Dean S. Anderson) lack of understanding of it, I decided to do a full, multi-threaded implementation in a modern version of Java. That version is now mostly operational and can successfully bootload MCS and has a partial implementation of the HSLA (High Speed Line Adapter) that works via TCP/IP connections. Due to a lack of documentation of the HSLA/HMLC cards, however, there has been some issues in simulating the hardware so that MCS is happy with it. We are able to get some terminal I/O but there are significant issues that prevent actually logging in to Multics so far.
The current focus is now on working through the issues between the hardware simulation and MCS.
The following table has links to various references (such as old manuals) that are actively in use for this phase of the project:
ID Description Link
AN85-01 SERIES 60 (LEVEL 68) MULTICS COMMUNICATION SYSTEM SYSTEM DESIGNERS' NOTEBOOK 4
AN87-00A SERIES 60 (LEVEL 68) MULTICS HARDWARE AND SOFTWARE FORMATS PROGRAM LOGIC MANUAL 5
AY34-02B 66/DPS, 68/DPS & DPS 8 DATANET 6641/6651/6661/6678 OPERATION 6
CC75-01 MULTICS ADMINISTRATORS' MANUAL - COMMUNICATIONS 7
CC92-01A SERIES 60 (LEVEL 68) MULTICS PROGRAMMERS' MANUAL - COMMUNICATIONS INPUT/OUTPUT 8
DC88-01 SERIES 60 (LEVEL 66) DATANET 6600 FRONT-END NETWORK PROCESSOR 9
DD01 Datanet 355/6600 Macro Assembler Program 10
FN01-03C DATANET 66 SYSTEM AND INSTALLATION MANUAL 11